A CMOS imager circuit includes a focal plane array of pixel circuits, each one of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that can include an output field effect transistor and a charge storage region connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level.
In a CMOS imager, the active elements of a pixel circuit perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc.
FIG. 1 illustrates a portion of a conventional CMOS imager 10. The illustrated imager 10 includes a pixel 20, one of many that are in a pixel array (not shown), connected to a column sample and hold circuit 40 via a pixel output line 32. The illustrated pixel 20 includes a photosensor 22 (illustrated as a photodiode for example purposes only), transfer transistor 24, floating diffusion region FD (illustrated as a photodiode 34 for example purposes only), reset transistor 26, source follower transistor 28 and row select transistor 30. The photosensor 22 is connected to the floating diffusion region FD by the transfer transistor 24 when the transfer transistor 24 is activated by a transfer control signal TX. The reset transistor 26 is connected between the floating diffusion region FD and an array pixel supply voltage VAApix. A reset control signal RST is used to activate the reset transistor 26, which resets the floating diffusion region FD (as is known in the art).
The source follower transistor 28 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage VAApix and the row select transistor 30. The source follower transistor 28 converts the stored charge at the floating diffusion region FD into an electrical output voltage signal VOPIX. The row select transistor 30 is controllable by a row select signal RS for selectively connecting the source follower transistor 28 and its output voltage signal VOPIX to the pixel output line 32.
A constant current source 38 provides a biasing current IVLN that is used to bias the pixel output line 32. The constant current source 38 is shared for all pixels 20 on the same column in the pixel array. Within the column sample and hold circuit 40, the pixel output line 32 is connected to a first capacitor 44 (having a first capacitance C1) thru a sample and hold reset signal switch 42. The sample and hold reset signal switch 42 is controlled by a sample and hold reset control signal SHR. The pixel output line 32 is connected to a second capacitor 54 (having a second capacitance C2) thru a sample and hold pixel signal switch 52. The sample and hold pixel signal switch 52 is controlled by a sample and hold pixel control signal SHS. The switches 42, 52 are typically MOSFET transistors.
The second terminal of the first capacitor 44 is connected to a clamping voltage vcl via a first clamping switch 47. The second terminal of the second capacitor 54 is also connected to the clamping voltage vcl by a second clamping switch 48. The clamping voltage vcl is used to place a charge on the two capacitors 44, 54 when it is desired to store reset and pixel signals, respectively (when the appropriate switches 47, 48 are closed by a control signal (not shown) and the appropriate sample and hold control signals SHR, SHS are generated). A crowbar switch 46 is used to read out the signals stored in the capacitors 44, 54 (when a crowbar signal cb is generated to close the switch 46).
Referring to FIGS. 1 and 2, the operation of the imager 10 is now described. In operation, the source follower transistor 28 acts as a buffer for the voltage on the floating diffusion region FD and drives the pixel output voltage signal VOPIX onto line 32 when the row select control signal RS is asserted. The pixel readout operation is initiated when the reset control signal RST is pulsed, which activates the reset transistor 26 and resets the floating diffusion region FD to the array pixel supply voltage VAApix. Then, the pixel output voltage signal VOPIX (i.e., reset level) is sampled and stored on the first capacitor 44 at the falling edge of the SHR pulse.
Next, the transfer transistor control signal TX is pulsed to transfer any charge accumulated in the photosensor 22 to the floating diffusion region FD. This will result in a voltage step on the floating diffusion region FD, where the size of the step depends on the conversion gain of the floating diffusion region FD. When the charge transfer is complete, the transfer transistor control signal TX is de-asserted and the pixel output voltage signal VOPIX is sampled to store the pixel signal level on the second capacitor 54 at the falling edge of the SHS pulse. For further processing, the net signal level from the pixel is interpreted as the voltage difference on the capacitors 44, 54, which is shown as ΔVOPIX in FIGS. 1 and 2. A new integration period can be started by resetting the photosensor 22 by asserting the transfer transistor control signal TX and the reset control signal RST simultaneously; the resetting of the photosensor 22 is then followed by the accumulation of charge in the photosensor 22 (once the transfer transistor control signal TX is de-asserted).
FIG. 3 illustrates a portion of another conventional CMOS imager 110. The illustrated portion of the imager 110 includes a pixel circuit 20 connected to a column amplifier and sample and hold circuit 140 via a pixel output line 32. A constant current source 38 provides a biasing current IVLN that is used to bias the pixel output line 32. The column amplifier and sample and hold circuit 140 includes a column level amplifier 170, a first capacitor 154 (having a first capacitance C1), a second capacitor 144 (having a second capacitance C2), a sample and hold reset signal switch 142 (controlled by a sample and hold reset control signal SHR), a sample and hold pixel signal switch 152 (controlled by a sample and hold pixel control signal SHS), first and second clamping switches 47, 48 and a crowbar switch 46 (controlled by a crowbar signal cb).
The amplifier 170 is connected between the pixel output line 32 (to receive and amplify the pixel output signal VOPIX) and the remaining sampling circuitry to reduce the total noise referenced to the pixel output. FIG. 4 illustrates a timing diagram for the portion of the imager 110, when the amplifier 170 is an inverting voltage amplifier. Referring to FIGS. 3 and 4, the operation of the imager 110 is now described. The row select control signal RS is set high to activate the row select transistor 30. The pixel readout operation is initiated when the reset control signal RST is pulsed, which activates the reset transistor 26 and resets the floating diffusion region FD to the array pixel supply voltage VAApix. The column level amplifier 170 is reset (by the pulsing of the reset amplifier control signal RST_AMP) after the floating diffusion region FD has been reset and the reset level of the amplifier 170 (referred to herein as VOAMP—RST) is sampled onto the second capacitor 144 via switch 142 at the falling edge of the SHR pulse.
Next, the transfer transistor control signal TX is pulsed to transfer any charge accumulated in the photosensor 22 to the floating diffusion region FD. This will result in a voltage step on the floating diffusion region FD, where the size of the step depends on the conversion gain of the floating diffusion region FD. When the charge transfer is complete, the transfer transistor control signal TX is de-asserted. When the amplifier output VOAMP (i.e., the amplified pixel signal level) has stabilized, the amplifier output VOAMP is sampled onto the first capacitor 154 via switch 152 at the falling edge of the SHS pulse. Since the column amplifier 170 has voltage gain of −A, the net signal level, interpreted as the voltage difference between the first and second capacitors 154, 144, translates to A·ΔVOPIX.
The imager 110 works well when the pixel output voltage signal VOPIX corresponds to a low pixel signal level, but not so well for higher signal levels (e.g., could cause increased noise in some situations). Moreover, the stored signals should not exceed the dynamic range of downstream circuitry (e.g., analog-to-digital converters), which could cause clipping. Accordingly, there exists a need and desire to increase intrascene dynamic range and signal-to-noise ratio in imagers.